1. Field of the Invention
The present invention relates generally to a memory device, and more particularly, to an electrically erasable and programmable read only memory (EEPROM) cell and a method for making such a memory cell.
2. Description of the Related Art
Electrically erasable programmable read only memory (EEPROM) cells are widely used in semiconductor industry. As is well known in the art, a conventional floating gate EEPROM cell includes a storage transistor and a select transistor, which results in a large memory cell size and low memory array density. Because of the floating gate structure, a conventional EEPROM cell needs to undergo double-poly processes for fabricating its floating gate and control gate. This makes the fabrication process of a conventional EEPROM cell complicate and expensive. The double-poly processes also make the fabrication process of the conventional EEPROM cells difficult to be integrated with the standard complementary metal oxide semiconductor (CMOS) logic process.
For conventional EEPROM array structures, isolation structures, such as isolation field oxide regions and isolation electrical lines, need to be used to isolate two adjacent EEPROM cells in order to overcome the program/erase disturb problems. The isolation field oxide regions of a conventional EEPROM array reduce the array density. Furthermore, the use of the isolation field oxide regions between adjacent EEPROM cells in the EEPROM array makes the surface of the EEPROM array scabrous, leading to a smaller process window for photoresist and etch processes. Moreover, the isolation electrical lines of the EEPROM array make the periphery circuit complex.
In view of the foregoing, there is a need for improved EEPROM cells that have small cell sizes, a single poly process, and compact array structures.